Posted by Saradwata Bandyopadhyay on 01-03-2025
Here is the solution for the above question =>
library IEEE;
use IEEE.std_logic_1164.all;
entity xnor_gate is
port(
I1 : in std_logic;
I2 : in std_logic;
OA : out std_logic);
end entity xnor_gate;
architecture behav of xnor_gate is
begin
OA <= I1 xnor I2;
end architecture behav;
You can directly download the Source Code and the Model Sim application from the
links below =>
Login to Comment.