library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity half_sub is
port( A, B : in std_logic;
DIFF, Borrow : out std_logic);
end entity;
architecture dataflow of half_sub is
begin
DIFF <= A xor B;
Borrow <= (not A) and B;
end architecture;