Posted by Saradwata Bandyopadhyay on 01-03-2025
Here is the solution for the above question =>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BASIC_MUX is
port( I0, I1 ,X: in std_logic;
F : out std_logic);
end entity;
architecture dataflow of BASIC_MUX is
begin
F <= ((I0 and (not X)) or (I1 and X));
end dataflow;
You can directly download the Source Code and the Model Sim application from the
links below =>
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