library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
entity decoder_case is port( din : in STD_LOGIC_VECTOR(1 downto 0); 
dout : out STD_LOGIC_VECTOR(3 downto 0) ); 
end decoder_case; 
architecture decoder_case_arc of decoder_case is begin decoder : 
process (din) is begin case din is when "00" => dout <= "1000"; 
when "01" => dout <= "0100"; 
when "10" => dout <= "0010"; 
when others => dout <= "0001"; 
end case; 
end process decoder; 
end decoder_case_arc;