library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_subtractor_case is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
d : out std_logic;
br : out std_logic);
end full_subtractor_case;
architecture Behavioral of full_subtractor_case is
begin
process(a,b,c)
begin
if(a='0' and b='0' and c='0')then
d<='0';
br<='0';
elsif( a='0' and b='0' and c='1')then
d<='1';
br<='1';
elsif( a='0' and b='1' and c='0')then
d<='1';
br<='1';
elsif( a='0' and b='1' and c='1')then
d<='0';
br<='1';
elsif( a='1' and b='0' and c='0')then
d<='1';
br<='0';
elsif( a='1' and b='0' and c='1')then
d<='0';
br<='0';
elsif( a='1' and b='1' and c='0')then
d<='0';
br<='0';
else
d<='1';
br<='1';
end if;
end process;
end Behavioral;